Parallel In Serial Out Shift Register
Category: Digital Circuits
Designer: RANA MUHAMMAD ADNAN KHALIL
Notes
This circuit is designed and simulated in Proteus 7.10. This is a simple circuit for demonstration of parallel to serial shift register. The IC used for this purpose is 74HC166. The working of this IC / circuit is given below. 1. There are four (4) control pins of 74HC166, which are clock (CLK), clock inhibit (INH) which is active low, shift data or load data (SH/LD) LD is active low and SH is active high, and last is master reset (MR) which is also active low. 2. One is serial input (SI) pin, you can ignore this pin if you are using parallel inputs. 3. One is serial output (SO) pin. 4. Eight (8) parallel input pins from D0 to D7. 5. The default setting should be: a) MR should be high. b) INH should be low. c) SH/LD should be high. 6. The parallel to shift sequance is: a) First of all set the data to the parallel inputs at D0 to D7 pins. b) To load this parallel data, change SH/LD from high to low state and give a clock pulse. The data is loaded at rising edge of clock. b) To shift this parallel data to serial output, change SH/LD from low to high state. c) Now give clock pulses, and data is serially transmitted from D7 to D0, which is shown in animation. Download these files to perform further experiments.